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Landscape of Synaptic Weight Memories
November 11 @ 12:00 pm - 1:00 pm
The Electron Devices Society (EDS), Northern Virginia/Washington Jt. Sections Chapters joined with The Nanotechology Council (NTC) are pleased to host an EDS Distinguished Lecture presented by Prof. Shimeng Yu, School of Electrical and Computer Engineering, Georgia Institute of Technology. Please register to receive the WebEx link the day before the event. —————————————————————————— Analog multilevel memories are the enabling device technologies for hardware acceleration of neuro-inspired computing workloads. In this lecture, we will survey the landscape of the emerging non-volatile memories that could serve the synaptic weights with a focus on resistive and ferroelectric devices. We will highlight the key device properties that are required for on-chip inference and/or training of deep neural network (DNN) models. We will use a multi-bit RRAM test vehicle to characterize the variability/reliability at array-level for inference. Then we will introduce an end-to-end benchmark framework DNN+NeuroSim to that is interfaced with PyTorch to evaluate versatile device technologies for DNN inference. Hybrid precision synapse that combines non-volatile memories with volatile capacitor is also presented to achieve in-situ training accuracy that is comparable with software. We will also showcase the integration of RRAM with peripheral CMOS at 40nm for a complete compute-in-memory prototype chip. Future research directions will be discussed. Speaker(s): Prof. Shimeng Yu, Virtual: https://events.vtools.ieee.org/m/284899